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Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture.
Chun Xue
Zili Shao
Meilin Liu
Mei Kang Qiu
Edwin Hsing-Mean Sha
Published in:
ICPADS (1) (2006)
Keyphrases
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multi core architecture
energy efficient
scheduling problem
data transfer
resource allocation
computing power
memory requirements
computational power
general purpose
multi core processors
digital signal processor