Brad Vest

Publication Activity (10 Years)

Years Active: 1998-2015
Publications (10 Years): 0

Top Topics

Close Proximity

Design Considerations

Top Venues

Hot Chips Symposium

Publications

Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang
Arria™ 10 device architecture. CICC (2015)
Brad Vest, Sean Atsatt, Mike Hutton
Design of a high-density SoC FPGA at 20nm. Hot Chips Symposium (2014)
Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis
MAX II: A low-cost, high-performance LUT-based CPLD. CICC (2004)
Paul Leventis, Mark Chan, Michael Chan, David M. Lewis, Behzad Nouban, Giles Powell, Brad Vest, Myron Wong, Renxin Xia, John Costello
Cyclone ™: a low-cost, high-performance FPGA. CICC (2003)
Brad Vest, Gwen Liang, Mark Chan, Eric Chun, Mark Fiester, Weiying Ding, Edmond Lau, Guu Lin, Behzad Nouban, Dirk Reese, Mian Smith, Nghia Tran, Stephanie Wong, Michael Woo, Myron Wong, John Costello
A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming. CICC (1999)
Dirk Reese, Eric Chun, Sammy Cheung, Edmond Lau, Michael Chu, Gwen Liang, Nghia Van Tran, Brad Vest, Richard Smolen, Minchang Liang, Seshan Sekariapuram, Behzad Nouban, Myron Wong, John Costello, John Turner
A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability. CICC (1998)