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A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability.

Dirk ReeseEric ChunSammy CheungEdmond LauMichael ChuGwen LiangNghia Van TranBrad VestRichard SmolenMinchang LiangSeshan SekariapuramBehzad NoubanMyron WongJohn CostelloJohn Turner
Published in: CICC (1998)
Keyphrases
  • low cost
  • single chip
  • input output
  • general purpose
  • high speed
  • power consumption
  • main memory
  • data transfer
  • network simulator
  • analog vlsi
  • floating gate
  • neural network
  • low power
  • circuit design
  • database
  • low voltage