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Bert Oude-Essink
ORCID
Publication Activity (10 Years)
Years Active: 2016-2024
Publications (10 Years): 4
Top Topics
Clock Frequency
Intel Xeon
Phase Locked Loop
Markov Processes
Top Venues
IEEE J. Solid State Circuits
VLSI Technology and Circuits
ISSCC
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Publications
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Sundeep Javvaji
,
Muhammed Bolatkale
,
Shagun Bajoria
,
Robert Rutten
,
Bert Oude-Essink
,
Koen Beijens
,
Kofi A. A. Makinwa
,
Lucien J. Breems
A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme.
IEEE J. Solid State Circuits
59 (4) (2024)
Sundeep Javvaji
,
Muhammed Bolatkale
,
Shagun Bajoria
,
Robert Rutten
,
Bert Oude-Essink
,
Koen Beijens
,
Kofi A. A. Makinwa
,
Lucien J. Breems
A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW.
VLSI Technology and Circuits
(2023)
Lucien J. Breems
,
Muhammed Bolatkale
,
Hans Brekelmans
,
Shagun Bajoria
,
Jan Niehof
,
Robert Rutten
,
Bert Oude-Essink
,
Franco Fritschij
,
Jagdip Singh
,
Gerard Lassche
15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW.
ISSCC
(2016)
Lucien J. Breems
,
Muhammed Bolatkale
,
Hans Brekelmans
,
Shagun Bajoria
,
Jan Niehof
,
Robert Rutten
,
Bert Oude-Essink
,
Franco Fritschij
,
Jagdip Singh
,
Gerard Lassche
A 2.2 GHz Continuous-Time ΔΣ ADC With -102 dBc THD and 25 MHz Bandwidth.
IEEE J. Solid State Circuits
51 (12) (2016)