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B. Jhnanesh Somayaji
Publication Activity (10 Years)
Years Active: 2016-2017
Publications (10 Years): 2
Top Topics
High Voltage
Distributed Architecture
Virtual Instrument
Association Rules
Top Venues
ISED
J. Low Power Electron.
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Publications
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B. Jhnanesh Somayaji
,
M. S. Bhat
Triple Reduced Surface Field Drain Extended MOS Device Design and Its RF Performance Evaluation for Sub-Micron RF SoC Platform.
J. Low Power Electron.
13 (4) (2017)
B. Jhnanesh Somayaji
,
M. S. Bhat
Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications.
ISED
(2016)