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Avaneesh K. Dubey
ORCID
Publication Activity (10 Years)
Years Active: 2018-2021
Publications (10 Years): 4
Top Topics
Design Process
Low Voltage
Mixed Signal
Power Dissipation
Top Venues
J. Circuits Syst. Comput.
Microelectron. J.
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Publications
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Vikrant Varshney
,
Avaneesh K. Dubey
,
R. K. Nagaria
Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications.
J. Circuits Syst. Comput.
30 (11) (2021)
Avaneesh K. Dubey
,
R. K. Nagaria
Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect.
J. Circuits Syst. Comput.
28 (9) (2019)
Avaneesh K. Dubey
,
R. K. Nagaria
Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique.
J. Circuits Syst. Comput.
27 (13) (2018)
Avaneesh K. Dubey
,
R. K. Nagaria
Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load.
Microelectron. J.
78 (2018)