Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load.
Avaneesh K. DubeyR. K. NagariaPublished in: Microelectron. J. (2018)
Keyphrases
- low power
- high speed
- single chip
- low cost
- power consumption
- cmos technology
- low power consumption
- power reduction
- vlsi architecture
- mixed signal
- logic circuits
- ultra low power
- gate array
- power dissipation
- vlsi circuits
- digital signal processing
- high power
- image sensor
- wireless transmission
- energy dissipation
- nm technology
- cmos image sensor
- real time
- low voltage
- design process
- frame rate
- signal processor