Adib Nahiyan

Publication Activity (10 Years)

Years Active: 2016-2021
Publications (10 Years): 16

Top Topics

Pattern Generation

Information Flows

Tamper Detection

Top Venues

ACM Trans. Design Autom. Electr. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

M. Sazadur Rahman, Adib Nahiyan, Fahim Rahman, Saverio Fazzari, Kenneth Plaks, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks. ACM Trans. Design Autom. Electr. Syst. 26 (4) (2021)
Adib Nahiyan, Jungmin Park, Miao Tony He, Yousef Iskander, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation. ACM Trans. Design Autom. Electr. Syst. 25 (3) (2020)
Huanyu Wang, Qihang Shi, Adib Nahiyan, Domenic Forte, Mark M. Tehranipoor
A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, Mark M. Tehranipoor
SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment. VTS (2020)
Md. Mahbub Alam, Adib Nahiyan, Mehdi Sadi, Domenic Forte, Mark M. Tehranipoor
Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation. ACM Trans. Design Autom. Electr. Syst. 25 (4) (2020)
Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev, Yier Jin, Mark M. Tehranipoor
RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level. VTS (2019)
Adam Duncan, Grant Skipper, Andrew Stern, Adib Nahiyan, Fahim Rahman, Andrew Lukefahr, Mark M. Tehranipoor, Martin Swany
FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection. HOST (2019)
Adib Nahiyan, Farimah Farahmandi, Prabhat Mishra, Domenic Forte, Mark M. Tehranipoor
Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (6) (2019)
Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev, Yier Jin, Mark M. Tehranipoor
RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level. CoRR (2019)
M. Sazadur Rahman, Adib Nahiyan, Sarah Amir, Fahim Rahman, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor
Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design. IACR Cryptol. ePrint Arch. 2019 (2019)
Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark M. Tehranipoor
Hardware Trojan Detection through Information Flow Security Verification. CoRR (2018)
Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark M. Tehranipoor
Security vulnerability analysis of design-for-test exploits for asset protection in SoCs. ASP-DAC (2017)
Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark M. Tehranipoor
Hardware trojan detection through information flow security verification. ITC (2017)
Animesh Chhotaray, Adib Nahiyan, Thomas Shrimpton, Domenic Forte, Mark M. Tehranipoor
Standardizing Bad Cryptographic Practice: A Teardown of the IEEE Standard for Protecting Electronic-design Intellectual Property. CCS (2017)
Kan Xiao, Adib Nahiyan, Mark M. Tehranipoor
Security Rule Checking in IC Design. Computer 49 (8) (2016)
Adib Nahiyan, Kan Xiao, Kun Yang, Yier Jin, Domenic Forte, Mark M. Tehranipoor
AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs. DAC (2016)