HLDVT

Publications

2017

Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
RTL level trace signal selection and coverage estimation during post-silicon validation. HLDVT (2017)
Tonmoy Roy, Michael Hsiao
Reachability analysis in RTL circuits using k-induction bounded model checking. HLDVT (2017)
Sophia Balkovski, Ian G. Harris
Designing cyber-physical systems from natural language descriptions. HLDVT (2017)
Zahra Shirmohammadi, Hadi Zamani Sabzi, Seyed Ghassem Miremadi
3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs. HLDVT (2017)
Keerthikumara Devarajegowda, Wolfgang Ecker
On generation of properties from specification. HLDVT (2017)
Maral Amir, Tony Givargis
HES machine: Harmonic equivalent state machine modeling for cyber-physical systems. HLDVT (2017)
Zhongqi Cheng, Tim Schmidt, Guantao Liu, Rainer Dömer
Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study. HLDVT (2017)
Michele Lora
Validation of HMI applications for industrial smart display. HLDVT (2017)
Masahiro Fujita
An approach to approximate computing: Logic transformations for one-minterm changes in specification. HLDVT (2017)
Daniela De Venuto, Giovanni Mezzina, V. L. Gallo
Design and implementation of FPGA-based muscle conduction velocity tracker in dynamic contractions during the gait. HLDVT (2017)
Siroos Madani, Kasem Khalil, Bappaditya Dey, Devante Bonton, Magdy A. Bayoumi
Repair techniques for aged TSVs in 3D integrated circuits. HLDVT (2017)
Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi
A novel SAT-based ATPG approach for transition delay faults. HLDVT (2017)
Pankaj Moharikar, Jayakrishna Guddeti
Automated test generation for post silicon microcontroller validation. HLDVT (2017)
Florenc Demrozi, Riccardo Zucchelli, Graziano Pravadelli
Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL. HLDVT (2017)
Guy Barash, Eitan Farchi
A randomized algorithm for constructing cross-feature tests from single feature tests. HLDVT (2017)
2017 IEEE International High Level Design Validation and Test Workshop, HLDVT 2017, Santa Cruz, CA, USA, October 5-6, 2017 HLDVT (2017)

2016

2012