SIGARCH Comput. Archit. News

Publications

volume 44, number 1, 2016

Lena E. Olson, Mark D. Hill
Probabilistic Directed Writebacks for Exclusive Caches. SIGARCH Comput. Archit. News 44 (1) (2016)
Hadi Asgharimoghaddam, Nam Sung Kim
SpinWise: A Practical Energy-Efficient Synchronization Technique for CMPs. SIGARCH Comput. Archit. News 44 (1) (2016)
Mark Thorson
Internet Nuggets. SIGARCH Comput. Archit. News 44 (1) (2016)

volume 44, number 4, 2016

Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao
An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division. SIGARCH Comput. Archit. News 44 (4) (2016)
Jubee Tada, Maiki Hosokawa, Ryusuke Egawa, Hiroaki Kobayashi
Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units. SIGARCH Comput. Archit. News 44 (4) (2016)
Fatemeh Eslami, Steven J. E. Wilton
An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug. SIGARCH Comput. Archit. News 44 (4) (2016)
Chengzhe Li, Lai Yoong Yee, Hiroshi Maruyama, Yoshiki Yamaguchi
FPGA-based Volleyball Player Tracker. SIGARCH Comput. Archit. News 44 (4) (2016)
Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung
Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. SIGARCH Comput. Archit. News 44 (4) (2016)
Jiayi Sheng, Qingqing Xiong, Chen Yang, Martin C. Herbordt
Collective Communication on FPGA Clusters with Static Scheduling. SIGARCH Comput. Archit. News 44 (4) (2016)
Susumu Mashimo, Thiem Van Chu, Kenji Kise
Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator. SIGARCH Comput. Archit. News 44 (4) (2016)
Ernst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars
An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping with BWAMEM. SIGARCH Comput. Archit. News 44 (4) (2016)
Shohei Sassa, Kenji Kanazawa, Shaowei Cai, Moritoshi Yasunaga
An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search. SIGARCH Comput. Archit. News 44 (4) (2016)
Ryohei Kobayashi, Tomohiro Misono, Kenji Kise
A High-speed Verilog HDL Simulation Method using a Lightweight Translator. SIGARCH Comput. Archit. News 44 (4) (2016)
Oliver Knodel, Paul R. Genssler, Rainer G. Spallek
Migration of long-running Tasks between Reconfigurable Resources using Virtualization. SIGARCH Comput. Archit. News 44 (4) (2016)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News 44 (4) (2016)
Vinod Pangracious, Mulhim Al-Doori
Novel Three-Dimensional Embedded FPGA Technology and Achitecture. SIGARCH Comput. Archit. News 44 (4) (2016)
Erik H. D'Hollander
High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication. SIGARCH Comput. Archit. News 44 (4) (2016)
Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. SIGARCH Comput. Archit. News 44 (4) (2016)
Cuong Pham-Quoc, Biet Nguyen, Tran Ngoc Thinh
FPGA-based Multicore Architecture for Integrating Multiple DDoS Defense Mechanisms. SIGARCH Comput. Archit. News 44 (4) (2016)

volume 44, number 5, 2016

Xusheng Zhan, Yungang Bao, Christian Bienia, Kai Li
PARSEC3.0: A Multicore Benchmark Suite with Network Stacks and SPLASH-2X. SIGARCH Comput. Archit. News 44 (5) (2016)

volume 43, number 2, 2015

volume 43, number 4, 2015

volume 43, number 5, 2015

Mark Thorson
Internet Nuggets. SIGARCH Comput. Archit. News 43 (5) (2015)

volume 42, number 4, 2014

volume 42, number 5, 2014

Mark Thorson
Internet Nuggets. SIGARCH Comput. Archit. News 42 (5) (2014)
Atin Mukherjee, Amitabha Sinha, Debesh Choudhury
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation. SIGARCH Comput. Archit. News 42 (5) (2014)
Jean-Louis Lafitte
Entangled-Coupling. SIGARCH Comput. Archit. News 42 (5) (2014)