Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes.
Marcos B. S. TavaresSteffen KunzeEmil MatúsGerhard P. FettweisPublished in: ASAP (2008)
Keyphrases
- convolutional codes
- high speed
- channel coding
- variable length
- processor array
- vlsi architecture
- error correction
- design procedure
- low density parity check
- error propagation
- low power
- turbo codes
- ldpc codes
- soft decision
- video transmission
- source coding
- viterbi algorithm
- error resilient
- coded images
- error resilience
- unequal error protection
- wireless channels
- signal processing
- rate allocation
- additive white gaussian noise
- bit error rate
- design methodology
- frame rate
- decoding algorithm
- distributed video coding
- error control
- low complexity
- image quality