On the Verification of VDM Specification and Refinement with PVS.

Savi Maharaj Juan Bicarregui

Published in: ASE (1997)

Keyphrases

formal verification
model checking
formal specification
timed automata
asynchronous circuits
formal methods
verification method
database
decision trees
temporal logic
refinement process
functional verification
protocol specification
machine learning
user defined
theorem proving