On-Chip Impedance for Quantifying Parasitic Voltages During AC Electrokinetic Trapping.
Vahid FarmehiniWalter VarhueArmita SalahiAlexandra R. HylerJaka CemazarRafael V. DavalosNathan SwamiPublished in: IEEE Trans. Biomed. Eng. (2020)
Keyphrases
- transmission line
- high speed
- microstrip
- low cost
- high density
- analog vlsi
- arc consistency
- vlsi implementation
- physical design
- power system
- circuit design
- vlsi design
- high bandwidth
- single chip
- operating conditions
- constraint programming
- computational intelligence
- electric field
- learning rate
- evolvable hardware
- differential equations
- active power
- host computer