Impact of Pixel per Processor Ratio on Embedded SIMD Architectures.

Antonio Gentile D. Scott Wills

Published in: ICIAP (2001)

Keyphrases

single instruction multiple data
parallel architectures
parallel processing
highly parallel
real time

image pixels
smart camera
multi core processors
input image
high speed

embedded processors
massively parallel
parallel implementation
pixel wise
dynamic random access memory

single chip
high end
standard deviation
parallel algorithm
digital images