A Low Power BIST Architecture for FPGA Look-Up Table Testing.
Ehsan AtoofianZainalabedin NavabiPublished in: VLSI-SOC (2003)
Keyphrases
- low power
- high speed
- low cost
- single chip
- vlsi architecture
- low power consumption
- power consumption
- gate array
- hardware implementation
- digital signal processing
- power reduction
- reconfigurable hardware
- real time
- high power
- cmos technology
- mixed signal
- hardware architecture
- hardware design
- nm technology
- wireless transmission
- logic circuits
- hardware and software
- vlsi circuits
- pipelined architecture
- signal processing
- cmos image sensor
- signal processor
- xilinx virtex
- fpga technology
- power dissipation
- field programmable gate array
- image sensor
- data flow
- fpga device
- power saving
- design considerations