Low-Power Keyword Recognition Feature Extraction Circuit based on SRMFCC and Shared Multiplier for High Noise Background.
Zilong ZhangHaichuang YangXuan ZhangXiaoling DingXuetao WangYu GongBo LiuPublished in: ASICON (2021)
Keyphrases
- low power
- feature extraction
- high noise
- high speed
- logic circuits
- cmos technology
- power consumption
- low cost
- gate array
- power reduction
- power dissipation
- vlsi circuits
- delay insensitive
- low contrast
- pattern recognition
- low power consumption
- feature space
- mixed signal
- face recognition
- feature vectors
- real time
- low voltage
- nm technology
- image processing
- digital signal processing
- image sensor
- hardware implementation
- wavelet transform