A new code compression algorithm and its decompressor in FPGA-based hardware.
Wanderson Roger Azevedo DiasEdward David MorenoIsaac Nattan PalmeiraPublished in: SBCCI (2013)
Keyphrases
- compression algorithm
- hardware architecture
- hardware implementation
- hardware design
- field programmable gate array
- data compression
- image compression
- bitstream
- compression ratio
- compression scheme
- low cost
- hardware description language
- low bit rate
- embedded systems
- hardware architectures
- quadtree decomposition
- processor core
- cosine transform
- error detection
- java virtual machine
- computing systems
- arithmetic coding
- pattern matching algorithm
- huffman coding
- jpeg images
- multiscale
- application specific
- wavelet based image
- coding scheme
- embedded zerotree wavelet
- lossless data compression