A low-power calibration-free fractional-N digital PLL with high linear phase interpolator.
Fan YangHangyan GuoRunhua WangZherui ZhangJunhua LiuHuailin LiaoPublished in: A-SSCC (2016)
Keyphrases
- low power
- mixed signal
- power consumption
- low cost
- high speed
- low power consumption
- vlsi circuits
- single chip
- multi channel
- high power
- logic circuits
- vlsi architecture
- cmos technology
- wireless transmission
- camera calibration
- digital signal processing
- image sensor
- gate array
- power saving
- general purpose
- transfer function
- cmos image sensor