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A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver.

Mike Yun HeJohn Poulton
Published in: IEEE J. Solid State Circuits (2006)
Keyphrases
  • high speed
  • data sets
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  • data processing
  • pattern recognition
  • low cost
  • cloud computing
  • data acquisition
  • low voltage
  • duty cycle