Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation.
Bernhard HoppeGerd NeuendorfDoris Schmitt-LandsiedelJ. Will SpecksPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1990)
Keyphrases
- power dissipation
- low power
- logic circuits
- high speed
- analytical models
- power consumption
- cmos technology
- low cost
- chip design
- digital signal processing
- single chip
- nm technology
- network on chip
- power reduction
- signal processing
- finite state machines
- analytical model
- flip flops
- image sensor
- energy efficiency
- real time
- tunnel diode
- mixed signal
- focal plane
- pattern recognition
- computer vision