Optimal FPGA module placement with temporal precedence constraints.
Sándor P. FeketeEkkehard KöhlerJürgen TeichPublished in: DATE (2001)
Keyphrases
- resource constrained project scheduling problem
- precedence relations
- precedence constraints
- verilog hdl
- scheduling problem
- worst case
- temporal information
- dynamic programming
- optimization problems
- vertex cover
- optimal solution
- message passing
- setup times
- parallel machines
- hardware implementation
- temporal reasoning
- constraint satisfaction problems
- computer systems
- special case