A 655Mbps Successive-Cancellation Decoder for a 1024-bit Polar Code in 180nm CMOS.
Hye-Yeon YoonSeung-Jun HwangTae-Hwan KimPublished in: A-SSCC (2018)
Keyphrases
- reed solomon
- nm technology
- successive approximation
- random access memory
- magnetic tape
- error control
- high speed
- error correcting codes
- error correction
- cmos technology
- silicon on insulator
- error detection
- power consumption
- low complexity
- low cost
- low power
- metal oxide semiconductor
- address space
- ldpc codes
- fourier transform
- decoding algorithm
- protection scheme
- source code
- analog to digital converter
- rotation invariant
- low density parity check
- power dissipation
- error concealment
- logical operations
- vlsi architecture
- analog vlsi
- frequency domain
- decoding process
- turbo codes