Design of Low Power Parallel Multiplier.

Rahul M. Badghare Sanjiv Kumar Mangal Raghavendra B. Deshmukh Rajendra M. Patrikar

Published in: J. Low Power Electron. (2009)

Keyphrases

low power
single chip
high speed
vlsi architecture
power consumption
low cost
low power consumption
logic circuits
power dissipation
high power
design process
mixed signal
cmos technology
power reduction
gate array
parallel processing
wireless transmission
shared memory
floating point
computer architecture
real time