A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits.

Scott Hanson Dennis Sylvester David T. Blaauw

Published in: ISLPED (2006)

Keyphrases

low energy
high speed
cmos technology
electron microscopy
minimum energy
low power
protein folding
power dissipation
low voltage
x ray
activity recognition
coarse grained
fine grained
field effect transistors