Delay Estimation and Sizing of CMOS Logic Using Logical Effort With Slope Correction.
Cheng C. WangDejan MarkovicPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2009)
Keyphrases
- delay insensitive
- logical representation
- logical framework
- predicate calculus
- probabilistic logic
- logical operations
- lambda calculus
- truth values
- multi valued
- accurate estimation
- error analysis
- logic programming
- estimation algorithm
- low cost
- high speed
- distortion correction
- dynamic logic
- parameter estimation
- modal logic
- low power
- logical theories
- automated reasoning
- error detection
- estimation process
- belief revision
- error correction
- logic programs
- logical rules
- estimation accuracy
- random access memory
- chip design