Generalized interleaving network based on configurable QPP architecture for parallel turbo decoder.
Shuaijie WangJun MaGuanghui HeZhigang MaoPublished in: SiPS (2011)
Keyphrases
- multi processor
- master slave
- parallel architecture
- fpga implementation
- distributed processing
- parallel computers
- processor array
- multi core processors
- processing elements
- real time
- distributed video coding
- processing units
- parallel computing
- low complexity
- management system
- turbo codes
- shared memory
- software architecture
- level parallelism