A low-power ΣΔ ADC optimized for GSM/EDGE standard in 65-nm CMOS.
Hussein FakhouryChadi JabbourHasham KhushkVan Tam NguyenPatrick LoumeauPublished in: ISCAS (2011)
Keyphrases
- low power
- cmos technology
- power consumption
- single chip
- low cost
- high speed
- nm technology
- vlsi circuits
- power reduction
- low power consumption
- high power
- digital signal processing
- wireless transmission
- image sensor
- wide dynamic range
- analog to digital converter
- edge detection
- mixed signal
- logic circuits
- cmos image sensor
- real time
- ultra low power
- delay insensitive
- power management
- wifi
- signal processor
- rfid tags
- parallel processing
- image processing