A scalable sorting architecture based on maskable WTA/MAX circuit.

Shin-Hong Ou Chi-Sheng Lin Bin-Da Liu

Published in: ISCAS (4) (2002)

Keyphrases

high speed
real time
management system
analog vlsi
multi processor
competitive learning
circuit design
learning algorithm
software architecture
multiprocessor architecture
layered architecture
highly flexible
digital circuits
data flow
lightweight
low cost
information systems