A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors.
Ehsan AtoofianAmirali BaniasadiPublished in: IPDPS (2007)
Keyphrases
- multithreading
- prediction accuracy
- high speed
- low cost
- power consumption
- prediction model
- ibm power processor
- functional verification
- chip design
- communication protocol
- computational power
- lightweight
- evolvable hardware
- prediction error
- circuit design
- prediction algorithm
- physical design
- tcp ip
- power dissipation
- programmable logic
- parallel implementation