Login / Signup
Parallel Hardware Architectures for the Cryptographic Tate Pairing.
Guido Marco Bertoni
Luca Breveglieri
Pasqualina Fragneto
Gerardo Pelosi
Published in:
Int. J. Netw. Secur. (2008)
Keyphrases
</>
hardware architectures
computational power
hardware architecture
smart card
shared memory
parallel processing
distributed memory
data sets
information systems
image processing
signal processing
message passing
parallel implementation
key management