A 32-bit carry lookahead adder design using complementary all-N-transistor logic.

Gang-Neng Sung Chun-Ying Juan Chua-Chin Wang

Published in: ICECS (2008)

Keyphrases

high speed
case study
logic circuits
user interface
circuit design
chip design
real time
neural network
multi agent systems
design considerations
predicate logic
power dissipation
block cipher
shift register