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A 58.9-dB ACR, 85.5-dB SBA, 5-26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS.
Ming-Feng Huang
Ming-Ching Kuo
Tzu-Yi Yang
Xuan-Lun Huang
Published in:
IEEE J. Solid State Circuits (2013)
Keyphrases
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high speed
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domain specific
noise reduction
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