Sign in

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs.

Atsushi NoseTomohiro YamazakiHironobu KatayamaShuji UeharaMasatsugu KobayashiSayaka ShidaMasaki OdaharaKenichi TakamiyaShizunori MatsumotoLeo MiyashitaYoshihiro WatanabeTakashi IzawaYoshinori MuramatsuYoshikazu NittaMasatoshi Ishikawa
Published in: Sensors (2018)
Keyphrases
  • high speed
  • computer architecture
  • real time
  • chip design
  • computer vision
  • case study
  • single chip
  • physical design
  • high speed networks
  • parallel implementation
  • parallel computing