Breaking the on-chip latency barrier using SMART.
Tushar KrishnaChia-Hsin Owen ChenWoo-Cheol KwonLi-Shiuan PehPublished in: HPCA (2013)
Keyphrases
- high speed
- low cost
- low latency
- analog vlsi
- high density
- response time
- programmable logic
- prefetching
- high bandwidth
- physical design
- heterogeneous computing
- database
- chip design
- smart objects
- vlsi implementation
- single chip
- circuit design
- smart spaces
- smart grid
- smart environments
- low power
- wireless sensor networks
- evolutionary algorithm
- neural network