A 2D-DCT low-power architecture for H.261 coders.
E. ScopaAlberto LeoneRoberto GuerrieriGiorgio BaccaraniPublished in: ICASSP (1995)
Keyphrases
- low power
- vlsi architecture
- high speed
- power consumption
- low cost
- cmos technology
- mixed signal
- single chip
- nm technology
- wireless transmission
- real time
- high power
- coding scheme
- gate array
- vlsi circuits
- digital signal processing
- logic circuits
- entropy coding
- power dissipation
- power reduction
- discrete cosine transform
- multi channel
- subband
- video data
- image coder
- image compression
- delay insensitive
- video compression
- low complexity