18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.
Jong-Chern LeeJihwan KimKyung Whan KimYoung Jun KuDae Suk KimChunseok JeongTae Sik YunHongjung KimHo Sung ChoYeon Ok KimJae-Hwan KimJin Ho KimSangmuk OhHyun Sung LeeKi Hun KwonDong Beom LeeYoung Jae ChoiJeajin LeeHyeon Gon KimJun Hyun ChunJonghoon OhSeok Hee LeePublished in: ISSCC (2016)