A novel efficient FPGA architecture for HMMER acceleration.
Mohd Nazrin Md. IsaKhaled BenkridThomas ClaytonPublished in: ReConFig (2012)
Keyphrases
- hardware implementation
- low cost
- management system
- efficient implementation
- knowledge base
- data structure
- dedicated hardware
- software implementation
- pipelined architecture
- neural network
- systolic array
- reconfigurable hardware
- fpga implementation
- real time image processing
- hardware design
- design methodology
- computationally expensive
- software architecture
- genetic algorithm