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A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS Technology.
Hossein Ghasemian
Amin Bahrami
Ebrahim Abiri
Mohammad Reza Salehi
Published in:
Circuits Syst. Signal Process. (2021)
Keyphrases
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cmos technology
acquisition process
low power
power consumption
low cost
high speed
image acquisition
low voltage
mixed signal
low power consumption
single chip
image sensor
power dissipation
digital signal processing
design process
silicon on insulator
power reduction