Designing circuits with partial scan.

Vishwani D. Agrawal Kwang-Ting Cheng Daniel D. Johnson Tonysheng Lin

Published in: IEEE Des. Test (1988)

Keyphrases

high speed
scan data
real time
analog vlsi
logic synthesis
delay insensitive
logic circuits
image processing
neural network
decision trees
bayesian networks
feature selection
analog circuits
asynchronous circuits
learning algorithm
data mining
real world
scan path
database
vlsi circuits