Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL Designs.
Aman GoelKarem A. SakallahPublished in: DATE (2019)
Keyphrases
- empirical evaluation
- model checking
- hardware description language
- integrated circuit
- temporal logic
- model based diagnosis
- formal specification
- temporal properties
- finite state
- automated verification
- model checker
- computation tree logic
- finite state machines
- formal verification
- symbolic model checking
- partial order reduction
- verification method
- reachability analysis
- formal methods
- pspace complete
- timed automata
- bounded model checking
- concurrent systems
- transition systems
- field programmable gate array
- multi agent systems
- asynchronous circuits
- satisfiability problem
- search algorithm