Neural parallel-hierarchical-matching scheduler for input-buffered packet switches.
Francisco J. González-CastañoCristina López-BravoRafael Asorey-CachedaJosé M. Pousada CarballoPedro S. Rodríguez-HernándezPublished in: IEEE Commun. Lett. (2002)
Keyphrases
- buffer size
- neural network
- matching algorithm
- parallel implementation
- image matching
- network architecture
- packet scheduling
- parallel computing
- matching process
- parallel processing
- pattern matching
- packet loss
- massively parallel
- matching scheme
- input data
- graph matching
- feature matching
- hierarchical structure
- keypoints
- bio inspired
- learning rules
- computer architecture
- real time