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An 8MB level-3 cache in 32nm SOI with column-select aliasing.

Don WeissMichael DreesenMichael CiraulaCarson HenrionChris HeltRyan FreeseTommy MilesAnita KaregarRussell SchreiberBryan SchnellerJohn Wuu
Published in: ISSCC (2011)
Keyphrases
  • silicon on insulator
  • query processing
  • high resolution
  • high quality
  • selection algorithm