A low-power and performance-efficient SAR ADC design.
Nahid MirzaieAhmed AlzahmiChung-Ching LinInsoo KimGyung-Su ByunPublished in: ISOCC (2017)
Keyphrases
- low power
- single chip
- power consumption
- low cost
- low power consumption
- high speed
- logic circuits
- vlsi architecture
- cmos technology
- digital signal processing
- power dissipation
- gate array
- mixed signal
- vlsi circuits
- analog to digital converter
- design process
- power reduction
- wireless transmission
- real time
- nm technology
- design considerations
- long range
- efficient implementation
- high power
- ultra low power