Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition.
Saranyu ChattopadhyayFlorian LonsingLuca PiccolboniDeepraj SoniPeng WeiXiaofan ZhangYuan ZhouLuca P. CarloniDeming ChenJason CongRamesh KarriZhiru ZhangCaroline TrippelClark W. BarrettSubhasish MitraPublished in: CoRR (2021)
Keyphrases
- functional decomposition
- digital circuits
- hardware designs
- field programmable gate array
- low cost
- boolean functions
- logic circuits
- model checking
- real time
- parallel implementation
- hardware implementation
- hardware architecture
- square root
- finite state machines
- low power
- asymptotic analysis
- embedded systems
- dynamic programming
- database