Verification of Synchronous Circuits by Symbolic Logic Simulation.

Randal E. Bryant

Published in: Hardware Specification, Verification and Synthesis (1989)

Keyphrases

asynchronous circuits
delay insensitive
chip design
logic synthesis
digital circuits
model checking
logic circuits
high speed
logic programming
mathematical model
symbolic representation
shift register
low cost
bounded model checking
linear logic
analog circuits
model checker
modal logic