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A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells.
Mina Kim
Seojin Choi
Taeho Seong
Jaehyouk Choi
Published in:
IEEE J. Solid State Circuits (2016)
Keyphrases
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real time
high speed
low cost
high resolution
duty cycle
low resolution
load balancing
real time traffic
floating point
neural network
fpga device
packet loss
hardware implementation
peer to peer
fault tolerance
end to end delay
fractional order
end to end
packet loss rate
human retina
control system