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A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET.

Sae Kyu LeePaul N. WhatmoughNiamh MulhollandPatrick HansenDavid BrooksGu-Yeon Wei
Published in: ESSCIRC (2018)
Keyphrases
  • high speed
  • low power
  • dynamic range
  • random access memory
  • dynamic random access memory
  • power consumption
  • vision system
  • cmos technology