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A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction.
Muhammed Bolatkale
Robert Rutten
Hans Brekelmans
Shagun Bajoria
Yihan Gao
Bernard Burdiek
Lucien J. Breems
Published in:
ISSCC (2022)
Keyphrases
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error correction
high speed
clock frequency
error detection
data hiding
power consumption
barcode
error correcting
channel coding
cmos technology
ldpc codes
high frequency
sigma delta
nm technology
turbo codes
digital content
frequency band
motion estimation
analog to digital converter