An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS.
Paul CholletBenoit LarrasCyril LahuecFabrice SeguinMatthieu ArzelPublished in: NEWCAS (2017)
Keyphrases
- ultra low power
- neural network
- low power
- cmos technology
- low cost
- artificial neural networks
- power consumption
- back propagation
- high speed
- pattern recognition
- neural nets
- genetic algorithm
- neural network model
- nm technology
- associative memory
- multi layer
- multilayer perceptron
- recurrent neural networks
- bp neural network
- self organizing maps
- single chip
- fault diagnosis
- maximum clique
- independent set
- fermentation process
- fuzzy logic