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A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology.
Sangdon Jung
Jaehong Jung
Byungki Han
Seunghyun Oh
Jongwoo Lee
Published in:
A-SSCC (2019)
Keyphrases
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cmos technology
power consumption
low power
clock frequency
power dissipation
power reduction
low cost
spl times
high speed
silicon on insulator
low voltage
parallel processing
clock gating
power management
mixed signal
hardware implementation
embedded dram